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Intellectual Ventures I, LLC v. Lenovo Group Ltd.

United States District Court, D. Massachusetts

April 4, 2019

Intellectual Ventures I, LLC;
v.
Lenovo Group Ltd., Lenovo United States Inc., LenovoEMC Products USA, LLC, and EMC Corp., Defendants. Intellectual Ventures II, LLC, Plaintiffs, Intellectual Ventures I, LLC; Intellectual Ventures II, LLC, Plaintiffs,
v.
NetApp, Inc., Defendant.

          MEMORANDUM AND ORDER

          PATTI B. SARIS Hon. Patti B. Saris Chief United States District Judge.

         INTRODUCTION

         Intellectual Ventures I, LLC and Intellectual Ventures II, LLC (collectively, “IV”) bring this patent infringement action alleging that Defendant EMC Corporation (“EMC”) infringes claim 11 of U.S. Patent No. 6, 516, 442 (the “'442 patent”). The Patent Trial and Appeal Board (“PTAB”) invalidated independent claim 1 of the '442 patent as obvious during inter partes review (“IPR”). EMC now moves for summary judgment on the invalidity of dependent claim 11 on two grounds: (1) IV is collaterally estopped from asserting claim 11 or (2) there is no genuine dispute that claim 11 is invalid as obvious under 35 U.S.C. § 103(a) over U.S. Patent No. 5, 490, 250 (“Reschke”). Because IV is collaterally estopped from asserting claim 11, the Court ALLOWS EMC's motion for summary judgment on the invalidity of claim 11 of the '442 patent (Docket No. 175).

         BACKGROUND

         A. The '442 Patent

         The Court assumes familiarity with the underlying patent from the prior claim construction opinion (Docket No. 236). As background, the '442 patent relates to a type of computer architecture known as a symmetric multiprocessor system or shared-memory multiprocessor system (“SMP”). '442 patent, col. 1, ll. 17-18, 65-66. In a conventional SMP, two or more processors are connected to a shared memory device via one shared “bus” - or communication channel. See Id. at col. 1, ll. 18-21. The claimed system of the '442 patent seeks to scale the classic SMP and solve for a “bottleneck” problem by using a “switched fabric” for data transfers which provides multiple concurrent buses for transactions between the processors and shared memory. See Id. at col. 1, ll. 50-53. Each component - including the switches in the switch fabric, microprocessors, and memory - communicates with a corresponding “interface.” So in the '442 system, processors and the shared memory device exchange data with and communicate through microprocessor and memory interfaces. See Id. at col. 2, ll. 59-67. Independent claim 1 of the '442 patent states:

1. A shared-memory multi-processor system comprising:
a switch fabric configured to switch packets containing data;
a plurality of channels configured to transfer the packets;
a plurality of switch interfaces configured to exchange the packets with the switch fabric, exchange the packets over the channels, and perform error correction of the data in the packets exchanged over the channels;
a plurality of microprocessor interfaces configured to exchange the data with a plurality of microprocessors, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels; and
a memory interface configured to exchange the data with a memory device, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels.

Id. at claim 1. Dependent claim 11 adds: “The shared-memory multi-processor system of claim 1 further comprising the microprocessors and the memory device.” Id. at claim 11.

         B. PTAB IPR of ...


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