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Intellectual Ventures I, LLC v. Lenovo Group. Ltd.

United States District Court, D. Massachusetts

March 13, 2019

Intellectual Ventures I, LLC; Intellectual Ventures II, LLC, Plaintiffs,
v.
Lenovo Group Ltd., Lenovo United States Inc., LenovoEMC Products USA, LLC, and EMC Corp., Defendants. Intellectual Ventures I, LLC; Intellectual Ventures II, LLC, Plaintiffs,
v.
NetApp, Inc., Defendant.

          MEMORANDUM AND ORDER ON CLAIM CONSTRUCTION

          PATTI B. SARIS, CHIEF UNITED STATES DISTRICT JUDGE

         INTRODUCTION

         Intellectual Ventures (“IV”) accuses several technology companies[1] of infringing U.S. Patent No. 6, 516, 442 (“the ‘442 patent”) entitled “Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system.”

         IV asserts claims 2, 8, 11, 25, and 31 against Defendants. Independent claim 1 states:

1. A shared-memory multi-processor system comprising:
a switch fabric configured to switch packets containing data;
a plurality of channels configured to transfer the packets; a plurality of switch interfaces configured to exchange the packets with the switch fabric, exchange the packets over the channels, and perform error correction of the data in the packets exchanged over the channels;
a plurality of microprocessor interfaces configured to exchange the data with a plurality of microprocessors, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels; and
a memory interface configured to exchange the data with a memory device, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels.

         Dependent claim 2 states:

2. The shared-memory multi-processor system of claim 1 wherein the interfaces are configured to add error correction codes to the packets being transferred over the channels to check the error correction codes in the packets being received over the channels and to transfer a retry request if one of the packets being received has an error.

         ‘442 patent, claims 1 and 2 (emphasis added). The disputed terms are underlined. The parties dispute the claim construction of three terms: “packet, ” “error correction, ” and “error correction code.” The Court held a non-evidentiary Markman hearing on November 16, 2018.

         BACKGROUND

         A. The ‘442 patent

          The ‘442 patent relates to a type of computer architecture known as a symmetric multiprocessor system or “shared-memory multi-processor system” (“SMP”). ‘442 patent at col. 1, ll. 17-18, 65-66. In a conventional SMP, two or more processors are connected to a shared memory device via one shared “bus” - or communication channel. See id. at col. 1, ll. 18-21. A processor retrieves data from memory to perform computations, and then sends information back to memory. These transactions between the processors and the memory take place one at a time over the shared bus. See id. at col. 1, ll. 30-32. The scalability of a conventional SMP is limited because “[a]s more processors are added [to the SMP], eventually system performance is limited by the saturation [i.e., bottlenecking] of the shared system bus.” Id. at col. 1, ll. 37-39.

         The ‘442 patent solves this problem by using a “switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory.” Id. at col. 1, ll. 50-53. Parties have agreed that the term “switch fabric” should be construed to mean “a data switching circuitry having a matrix or similar arrangement of interconnections.” Docket No. 195 at 6 n.1; Docket No. 196 at 9.

         Figure 3 of the ‘442 patent, reproduced below, shows the basic components of the claimed system using a Flow Control Unit (FCU 220). The system includes multiple processors (CPU 120), shared memory devices (SDRAM 1300-1303), and a switch fabric composed of multiple vertical and horizontal buses (320 and 340) and switches (380). Each component has a corresponding “interface.” In the ‘442 patent's system, processors (120) and (Image Omitted) memory devices (1300-1303) exchange data with, and communicate through, processor interfaces (DCIU 210) and memory interfaces (MCU 230). See ‘442 patent at col. 2, ll. 60-67.

         A “channel” is “a general-purpose, high-speed, point-to-point, full-duplex, bi-directional interconnect bus.” ‘Id. at col. 6, ll. 40-43. A “packet” is sent between Channel Interface Block (CIB) transceivers via a channel. Id. at col. 6, l. 65 - col. 7, l. 2. “A ‘packet' is the basic unit of transport over the channel.” Id. at col. 6, l. 53. In a preferred embodiment, a “packet is a single 80-bit frame (information unit) exchanged between CIBs” over a channel. Id. at col. 6, ll. 54-60. It includes data, control information, and error correction code (ECC).[2] Id. at col. 6, ll. 54-63.

         B. Prior Litigation on the ‘442 Patent (“HCC Litigation”)

         In July 2015, IV sued EMC customer HCC Insurance Holdings in the Eastern District of Texas, asserting the ‘442 patent along with three other patents. See Docket No. 179-1, Compl., Intellectual Ventures I LLC v. HCC Insurance Holdings, Inc., No. 6:15-cv-660 (E.D. Tex.). IV submitted an opening claim construction brief, arguing that all disputed terms should be given their “plain and ordinary meaning.” See Docket No. 195-7 (“HCC Litigation Opening Brief”) at 13-23. The magistrate judge held a Markman hearing and produced a report and recommendation construing disputed terms, including “packet, ” “error correction, ” and “error correction code.” The magistrate judge construed “packet” to mean “a basic unit of transport over a channel that includes data, control information, and error correction code”; “error correction” to mean “reconstruction of erroneous data”; and “error correction code” to mean a “code that can be used to correct erroneous data.” Docket No. 195-4 (“HCC Litigation R&R”) at 8-14. The case settled.

         C. PTAB IPR Review of the ‘442 Patent

         On May 27, 2016, EMC petitioned the PTAB for inter partes review (“IPR”) of the ‘442 patent, challenging the claims that had previously been asserted by IV against EMC's customer in the HCC Litigation (claims 1, 2, 5, 9, 10, 12, 24, 25, 28, 32, 33, and 34). See Docket No. 137-7 (“IPR Petition”). EMC based its petition, in part, on U.S. Patent No. 5, 490, 250 (“Reschke”), a patent that ...


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